• Company Confidential
  • $104,670.00 -157,460.00/year*
  • Austin, TX
  • Engineering
  • Full-Time
  • 103 E 5th St

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Role CPU Design Verification Engineer Duration 6 months Location ndash Austin, TX Position Details Description PositionRole Gate level simulation support for all projects. Enhance and maintain flows, testbenches and verifications plan related to gate level simulations. Manage all gate level simulation regressions and debug, including SDF annotated models. Coordinate with physical implementation and functional verification teams as needed. Deliver fsdbvectors to physical team as needed for performance and power analysis. Requirements Experience with gate level simulation support for CPU projects. Demonstrated experience to enhance and maintain flows, testbenches and verifications plan related to gate level simulations. Experience with gate level simulation regressions and debug, including SDF annotated models. Experience working with physical implementation and functional verification teams on CPU design activity. Demonstrated delivery of fsdbvectors to physical team as needed for performance and power analysis Please contact me if you need further information.
Associated topics: bsee, cpu, design, electronic, embedded, mems, qubit, rtl, rtos, surface mount

* The salary listed in the header is an estimate based on salary data for similar jobs in the same area. Salary or compensation data found in the job description is accurate.

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